5. Restrictions

LegUp has the following restrictions in this release.

5.1. Hybrid Flow

The processor-accelerator hybrid flow is currently limited to Intel FPGAs only in the full licensed version of LegUp.

5.2. Struct Support

LegUp automatically attempts to split up all structs into their individual elements, but this may not be possible in some cases. When there are structs that cannot be automatically split up, the user has to manually split them up in C, when targeting Xilinx, Lattice, Microsemi, and Achronix FPGAs. For more details, please refer to Structs section in Optimization Guide chapter.

5.3. Floating-point Support

LegUp currently supports floating-point operations for Intel FPGAs only.

5.4. Function Pipelining

When function pipelining feature is used (i.e., when one or more functions are added with Pipeline function constraint), a custom top-level function must be specified. The top-level function has to be one specified with Pipeline function constraint, or a wrapper function that simply calls multiple sub-functions that are all specified with Pipeline function constraint (Function Pipelining).

5.5. LegUp C Library

5.5.1. Bit-level Operation Library

When using the bit-level operation APIs, all index and width arguments must be constant integers (Bit-level Operation Library).

5.5.2. Streaming Library

A FIFO can only be written to (via fifo_write) by one function and read from (via fifo_read) by another function. It cannot be both written to and read by the same function. In addition, there cannot be multiple functions writing to the same FIFO or multiple functions reading from the same fifo.

5.6. Using Pre-existing Hardware Modules

LegUp allows connecting existing hardware modules to the hardware generated by LegUp. Currently, an existing hardware module that is connected to LegUp-generated hardware cannot access any memories. All arguments need to be passed in by value. An existing hardware module cannot be invoked in a pipelined section (within a pipelined loop/function). In addition, an existing hardware module cannot invoke other modules (functions or other custom Verilog modules).

5.7. Microsemi Support (Beta)

Support for Microsemi is still in beta for this release. Microsemi’s synthesis tool, Libero, currently does not support inferring ROMs (read-only memories) from a generic Verilog module when targeting their SmartFusion2 FPGA (Microsemi’s documentation). Thus any ROMs generated by LegUp will be synthesized into registers with Microsemi’s Libero. If there are large ROMs in the design, this can cause the circuit area to increase significantly.

Microsemi also does not support initializing memories during FPGA power up. Memories must be initialized via an external source or with FPGA logic. LegUp uses a memory initialzation file to initialize memories automatically when the FPGA is power up. Since this not supported for Microsemi, memory initialization will only work in simulation.

5.8. Achronix Support (Beta)

Support for Achronix is still in beta for this release. Memory inference is not yet supported (for both RAMs and ROMs). All memories will be synthesized into registers with Achronix’s CAD tool. If there are large RAMs/ROMs in the design, this can cause the circuit area to increase significantly.