6. Frequently Asked Questions¶
How is LegUp different from other high-level synthesis (HLS) tools?
LegUp is the only high-level synthesis tool that can target ALL FPGA Vendors (Intel, Xilinx, Lattice, Microsemi, and Achronix FPGAs). This means that you are not tied to a vendor specific HLS tool, many of which have very different design methodologies, constraints, and input languages. You can simply design your application once and target any FPGA you want! LegUp is also the only HLS tool that supports the use of Pthreads and OpenMP to create parallel hardware. This powerful feature allows one to write standard multi-threaded software, and automatically compile it to a multi-core hardware system. Lastly, LegUp can generate a complete SoC, comprising a processor and hardware accelerators, with a click of a single button.
Tell me more about Pthreads and OpenMP support.
Pthreads and OpenMP are popular parallel programming methodologies in software. The threads described in software gets compiled to execute on multiple processor cores. LegUp can take the same software program and automatically compile it to multiple hardware cores. This powerful technique allows one to create a multi-core hardware system directly from software, without any changes to the code. This feature is available both for a hardware-only system (without a processor) or for a processor-accelerator hybrid system.
Tell me more about the processor-accelerator hybrid flow.
Not all programs are amenable for hardware acceleration. One may want to have a processor for controlling the hardware, or to run an operating system, or just for ease-of-use. The processor-accelerator hybrid flow in LegUp allows one to accelerate a portion of the program while keeping the rest running in software on a processor. All that the user has to do is simply designate which function(s) to accelerate in hardware, and the rest is taken care of automatically. LegUp automatically partitions the program so that the designated function(s) and the descendant functions are compiled to hardware accelerators, with the remainder of the program is compiled to execute on an ARM processor. The tool automatically handles the software/hardware partitioning, and their communication interfaces and interconnect are also automatically generated. This flow allows one to generate a complete SoC, comprising a processor and hardware accelerators, directly from software. Note that this processor-accelerator hybrid flow is only available currently for Intel FPGAs in the full licensed version of LegUp.
What is the input language?
LegUp supports most of ANSI C, but it does not support recursive functions or dynamic memory. As mentioned above, it also supports Pthreads and OpenMP to create parallel hardware.
What is the output language?
Currently, LegUp only supports Verilog output.
Which FPGAs do you support?
LegUp supports Intel (Altera) Arria V, Cyclone IV, Cyclone V, Stratix IV, Stratix V, Xilinx Virtex 6, Virtex 7, Lattice ECP 5, Microsemi Fusion, and Achronix Speedster FPGA. These are the FPGAs that we have tested for, but the majority output that LegUp produces is generic and not tied to a particular FPGA. Hence it can be easily ported to other FPGAs as well.
How can I get support?