LegUp Computing Inc. was founded after 25 man-years of research in FPGA high-level synthesis and compute acceleration at the Department of Electrical and Computer Engineering, University of Toronto. We provide solutions for FPGA hardware acceleration, which can bring orders of magnitude improvement in computational throughput and energy efficiency compared to software executing on a processor.
We are world-leading researchers in FPGA high-level synthesis and compute acceleration. We have decades of FPGA experience and have more than 80 conference/journal publications and 20 patents in the field of FPGA architecture, CAD algorithms, and high-level synthesis.
Chief Executive Officer
Andrew Canis received the Ph.D. degree in computer engineering in 2015 from the University of Toronto, Toronto, Canada. During his studies, he held internships at Altera, Sun Microsystems Labs, and at Oracle Labs, where he researched circuit optimization algorithms. His research interests include high-level synthesis, reconfigurable computing, embedded system-on-chip design, and electronic design automation for FPGAs. He received the NSERC Alexander Graham Bell Canada Graduate Scholarship.
Chief Technology Officer
Jongsok (James) Choi is an expert in high-level synthesis and hardware/software co-design. He has been working with FPGAs over the last 9 years, where he has co-authored 15 top-tier conference/journal publications and a book chapter in the area of high-level synthesis, automatic System-on-Chip (SoC) design, and automatic synthesis of multi-threaded software to parallel hardware. He received his Ph.D degree in Computer Engineering in 2016 and his M.A.Sc. degree in 2012, both from the University of Toronto. Jongsok has previously worked at Intel, Qualcomm, Marvell Semiconductor, STMicroelectronics, and Blackberry.
Chief Operating Officer
Ruo Long (Lanny) Lian received the M.A.Sc degree in computer engineering in 2016 from the University of Toronto, where his research centered on streaming circuit synthesis and FPGA-based acceleration of neural network computation. Ruolong has interned at Altera, implementing high-speed ethernet transceiver IPs, and also at Google, working on large-scale data processing solutions. He received the Bell Graduate Scholarship during his M.A.Sc study.
Chief Scientific Advisor
Jason Anderson is a Professor with the Department of Electrical and Computer Engineering, U of T, and holds the Jeffrey Skoll Endowed Chair. He joined the Field-Programmable Gate Array (FPGA) Implementation Tools Group, Xilinx, Inc., San Jose, CA, USA, in 1997, where he was involved in placement, routing, and synthesis. He became a Principal Engineer at Xilinx in 2007 and joined the university in 2008. His research interests are all aspects of tools, architectures, and circuits for FPGAs. He has co-authored over 80 peer-reviewed research publications, holds 27 U.S. patents and is Program Co-Chair for FPL 2016 and Program Chair for ACM FPGA 2017.