Since the previous release of LegUp 5.1 last year, we have seen many users creating interesting projects using LegUp. We have also received lots of valuable feedback. Based on your feedback, we have added a number of new features to further improve the HLS design process with LegUp. We have also enhanced our tool’s reliability through bug fixes.
Prior to the commercial releases, LegUp has had 4 major releases for academic research and has been used by thousands of researchers around the world, making it the de-facto standard in high-level synthesis (HLS) research. In 2014, LegUp won the Community Award at the International Conference on Field Programmable Logic (FPL) for contributions to HLS research. LegUp has also been shown to produce state-of-the-art hardware.
We have brought all of the best features from our previous releases, and made LegUp even better by adding new features, as well as improving the quality of the generated hardware.
Here are just some of the highlights of what we have added for this release:
- SW/HW Co-simulation: uses your C-based software test bench to automatically verify the LegUp-generated RTL.
- A C++ FIFO template class to allow more flexible definition of FIFO data types.
- New FPGA device support for Intel Arria 10, Microsemi PolarFire, and Xilinx Virtex UltraScale+, in addition to the existing device support for Intel, Xilinx, Lattice, Microsemi, and Achronix FPGAs.
- Improved control-flow optimization.
- Improved memory partitioning.
LegUp 6.1 comes with a 30-day free trial period so that you can try out the tool. Please note that during the trial period, you may only use LegUp for evaluation purposes, and the generated hardware cannot be used in a commercial product. To purchase a full license, please contact us at email@example.com.
You can download LegUp here.
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