High-level synthesis using C++ works very well for designers describing data-flow applications like digital signal processing or video/image processing. But for certain control heavy applications, such as a bus controller, a designer will have trouble describing the cycle accurate behavior of the hardware in C++. We decided to help fix this problem by adding support for System C as an input language to LegUp HLS.
System C is a standard C++ library that allows a designer to specify cycle-accurate behavior. Typically System C is used for system-level modeling of a larger system. System C offers the advantage of faster simulation time than running RTL simulations while still being able to measure cycle-accurate behavior.
System C explicitly describes the cycle behavior of the application. There is no flexibility for the operations to be scheduled into different clock cycles like when C++ is used in LegUp HLS. This provides the user with very fine-grained control over the behavior of the generated hardware.
AHB-Lite Bus Slave Controller Example
For an example of a control-heavy application, we will implement a simplified AHB-Lite bus slave controller in System C. We will focus on how to implement the part of the bus protocol that requires cycle-accurate control: the error response code.
For background, the AHB-Lite bus protocol has two possible responses (HRESP) from the slave to the master. First, if the transaction was successful the HRESP will be OKAY (0) but if there was an error there will be a two cycle delay and HRESP will be ERROR (1). See the waveforms below:
The 2-cycle delay behavior when an error occurs is hard for a designer to express in typical LegUp HLS C++ code. But with System C, we can use the wait() function to introduce a 1-cycle delay.
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