Category: News


World’s Fastest Cloud-Hosted Memcached: 11M+ Ops/sec at 0.3 msec Latency with a Single AWS F1

By Jongsok Choi,

We are pleased to present the world’s fastest cloud-hosted Memcached on AWS using EC2 F1 (FPGA) instances. With a single F1 instance, LegUp’s Memcached server prototype achieves over 11M ops/sec, a 9X improvement over ElastiCache, at <300 μs latency. It offers 10X better throughput/$ and up to 9X lower latency compared to ElastiCache. Please refer to our 1-page handout for more details.

If you would like a demo of the Memcached server, please contact us at info@legupcomputing.com.

 

LegUpMemcachedHandout

 

LegUp Computing closes a seed-funding round led by Intel Capital

By Andrew Canis,

TORONTO, February 22, 2018 — LegUp Computing, Inc. announced today that it closed a seed funding round led by Intel Capital. LegUp offers a cloud platform that enables software developers to program, deploy, scale, and manage FPGA devices for accelerating high performance applications without requiring hardware expertise. The technology enables the next generation of low-latency and high-throughput computing on the vast amount of real-time data processed in the cloud. LegUp Computing, Inc., was spawned from years of research in the Dept. of Electrical and Computer Engineering at the University of Toronto to commercialize the award-winning open-source LegUp high-level synthesis tool.

LegUp Computing Team

LegUp Computing team from left to right: Omar Ragheb, Zhi Li, Dr. Andrew Canis, Ruolong Lian, Dr. Jongsok Choi, and University of Toronto Professor Jason Anderson (Photo: Jessica MacInnis)

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Synthesizing Streaming Floating-Point Cores with LegUp HLS — Publication in DATE 2018

By Jason Anderson,

A paper describing the use of LegUp HLS to synthesize hardware cores for floating-point computations from C-language software will appear in the 2018 ACM/IEEE Design Automation and Test in Europe (DATE) conference, to be held at Dresden, Germany, in March 2018.  The floating-point cores are fully IEEE 754 compliant, yet through software changes alone, can be tailored to application needs, for example, by reducing precision or eliminating exception checking, saving area and raising performance in non-compliant variants.  The IEEE-compliant cores synthesized by LegUp HLS compare favourably to custom RTL cores from FloPoCo and Altera/Intel, despite the LegUp-generated cores being synthesized entirely from software.  An advance copy of the paper, jointly authored by the University of Toronto and Altera/Intel, is available: PDF.

 

Using LegUp HLS to Synthesize a Deep CNN Inference Accelerator

By Jason Anderson,

A paper describing the synthesis of a deep convolutional neural network (CNN) inference accelerator from C software with LegUp HLS will appear at the 2017 IEEE International System-on-Chip Conference (SOCC), at Munich, Germany, in September 2017. The work showcases the use of LegUp’s unique Pthreads flow to convert parallel software threads into spatial hardware parallelism. The accelerator incorporates a novel approach for zero-weight skipping, leveraging the ability to prune CNN weights with little inference accuracy loss.

J. H. Kim, B. Grady, R. Lian, J. Brothers, J.H. Anderson, “FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software,” IEEE SOCC, 2017 (PDF).